Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs).
Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
Semiconductor devices exploit the electrical properties of semiconductor materials. The atomic structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or base current or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.
A semiconductor device contains active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions.
Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die is typically identical and contains circuits formed by electrically connecting active and passive components. The term “semiconductor die” as used herein refers to both the singular and plural form of the word, and accordingly can refer to both a single semiconductor device and multiple semiconductor devices. Back-end manufacturing involves singulating individual die from the finished wafer and packaging the die to provide structural support and environmental isolation.
One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller die size can be achieved by improvements in the front-end process resulting in die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.
One common technique of interconnecting a semiconductor die with a printed circuit board or other substrate involves the use of bumps. FIG. 1 illustrates a conventional semiconductor device 10 with flipchip type semiconductor die 12 having an active surface 13 and contact pads 14 formed on the active surface. An insulating or passivation layer 15 is formed over active surface 13 and contact pads 14. A portion of insulating layer 15 is removed by an etching process to expose contact pads 14. An insulating or dielectric layer 16 is formed over insulating layer 15 and the exposed contact pads 14. A portion of insulating layer 16 is removed by an etching process to expose contact pads 14. An electrically conductive layer 18 is conformally applied over the exposed contact pads 14 and insulating layer 16. Conductive layer 18 operates as an under bump metallization (UBM) layer electrically connected to contact pads 14. A conductive pillar 20 is formed over conductive layer 18.
A substrate or PCB 22 has one or more conductive layers 24 and laminated insulating or dielectric layers 26. An insulating layer 28 is formed over insulating layer 26 and conductive layer 24. A portion of insulating layer 28 is removed by patterning, exposure to ultraviolet (UV) light, and developing to expose conductive layer 24. A bump material 30 is deposited over conductive layer 24. Semiconductor die 12 is positioned over and mounted to substrate 22 using a pick and place operation with active surface 13 and conductive pillars 20 oriented toward the substrate. Conductive pillars 20 are metallurgically and electrically connected to conductive layer 24 with bump material 30.
FIG. 2 illustrates another conventional semiconductor device with flipchip type semiconductor die 12 having an active surface 13 and contact pads 14 formed on the active surface. An insulating or passivation layer 15 is formed over active surface 13 and contact pads 14. A portion of insulating layer 15 is removed by an etching process to expose contact pads 14. An insulating or dielectric layer 16 is formed over insulating layer 15 and the exposed contact pads 14. A portion of insulating layer 16 is removed by an etching process to expose contact pads 14. An electrically conductive layer 18 is conformally applied over the exposed contact pads 14 and insulating layer 16. Conductive layer 18 operates as a UBM layer electrically connected to contact pads 14. A bump material 31 is deposited over conductive layer 18.
A substrate or PCB 32 has one or more conductive layers 34 and laminated insulating or dielectric layers 36. An insulating layer 38 is formed over insulating layer 36 and conductive layer 34. A portion of insulating layer 38 is removed by patterning, exposure to UV light, and developing to expose conductive layer 34. A conductive seed layer 39 is formed over conductive layer 34. A conductive pad 40 is formed over conductive seed layer 39. Semiconductor die 12 is positioned over and mounted to substrate 32 using a pick and place operation with active surface 13 and bump material 31 oriented toward the substrate. Bump material 31 are metallurgically and electrically connected to conductive pads 40.
FIG. 3 illustrates another conventional semiconductor device with flipchip type semiconductor die 12 having an active surface 13 and contact pads 14 formed on the active surface. An insulating or passivation layer 15 is formed over active surface 13 and contact pads 14. A portion of insulating layer 15 is removed by an etching process to expose contact pads 14. An insulating or dielectric layer 16 is formed over insulating layer 15 and the exposed contact pads 14. A portion of insulating layer 16 is removed by an etching process to expose contact pads 14. An electrically conductive layer 18 is conformally applied over the exposed contact pads 14 and insulating layer 16. Conductive layer 18 operates as a UBM layer electrically connected to contact pads 14. A bump material 41 is deposited over conductive layer 18.
A substrate or PCB 42 has one or more conductive layers 44 and laminated insulating or dielectric layers 45. An insulating layer 46 is formed over insulating layer 45 and conductive layer 44. A portion of insulating layer 46 is removed by patterning, exposure to UV light, and developing to expose conductive layer 44. A conductive seed layer 47 is formed over conductive layer 44. A conductive pad 48 is formed over conductive seed layer 47. A solderability enhancement layer 49, such as Ni or Au, is formed over conductive pad 48. Semiconductor die 12 is positioned over and mounted to substrate 42 using a pick and place operation with active surface 13 and bump material 41 oriented toward the substrate. Bump material 41 are metallurgically and electrically connected to conductive pads 48 and solderability enhancement layer 49.
In each case of FIGS. 1-3, the bump interconnect structure is susceptible to de-wetting of the UBM and exhibits weak joints and reliability problems. For example, conductive pillar 20 of FIG. 1 induces high stress on semiconductor die 12, leading to cracking around the conductive pillar. Conductive pads 40 and 48 exhibit joint reliability issues due in part to the limited contact surface area between bump material 31 and 41 and the conductive pads, as shown in FIGS. 2 and 3. The cracking and joint reliability reduce manufacturing yield and increase cost.